Investigation of digital to analog converter to improve Integrated Circuits

The purpose of this study is to investigate a digital-to-analog converter to improve integrated circuits. This calibration eliminates redundant comparators and thus reduces the area. Reference voltage generators, which run on resistive ladders in conventional ADCs, are eliminated thanks to the use of CDAC with interpolation in comparators. The measured DNL and INL (with and without calibration) are shown in Figure 13. Prior to calibration, the DNL and INL each reach 3 LSBs. After calibration, they are reduced to 0.8 LSB. The measured range after calibration is shown in the figure. Here, the sampling frequency is 1 GS/s, and the input signal frequency is 501 MHz. The SNDR is 32.8 dB, resulting in 5.16 ENOB at Nyquist frequency.